Base part of the COINS compiler infrastructure
1. Position of the base part
The base part of COINS compiler infrastructure is composed of
modules that are inevitable in most compilers. The current
components of the base part are
- C analyzer
- Fortran analyzer
- HIR (High level intermediate representation) handler
- LIR (Low level intermediate representation) handler
- Symbol table handler
- Basic optimizer
- Basic parallelizer (do-all parallelizer)
- Flow analyzer
- HIR to LIR converter
- Sparc code generator
- Intel x86 code generator
- Code generator based on machine description
- Compiler driver
The COINS compiler has other specific function modules
that are constructed using the base part. Currently,
there are following modules:
- SSA optimizer
- SMP parallelizer
- SIMD parallelizer
- HIR to C translator
- LIR to C translator
In this document, overviews of HIR, LIR, symbol table, and
flow analyzer will be given.
2. Intermediate representation
In COINS, source program is translated to high level intermediate
representation HIR and then HIR is transformed to low level intermediate
representation LIR. Code generator for specific machine is constructed
from target machine description TMD and it generates object code for
the machine from LIR.
HIR is an abstract language that can represent the control structure and
data structure of the source program in language independent and machine
independent form. Transformations and analyses for optimization and
parallelization suitable to be designed on high level language are
performed on HIR.
LIR is an abstract language based on abstract register machine.
It has complete textual form and can be constructed from text stream
as well as from HIR. Transformations for optimization and parallelization
suitable to be designed on machine operation level are performed on LIR.
Most modules for handling LIR can be built in machine independent form.
All symbols in the source program and all symbols generated by the
compiler are registered in a table named symbol table. In HIR and LIR,
all symbols are represented by referring the corresponding symbol table
entry. All attributes of a symbol can be get from the symbol table.
3. Flow analysis
In optimization and parallelization, control flow information and
data flow information are required. The control flow analyzer decomposes
program into basic blocks and represents the control flow as a directed
graphs of basic blocks and provides various control flow information.
The data flow analyzer does analysis of define-use relations of variables
and computes various data flow information.
At present, the control flow analyzer and data flow analyzer are
provided for HIR as methods that can be called from any module.
4. Links for more information
As for more information, see the following documents: